The present invention generally relates to a power system for an electronic device and more particularly, to the insertion of decoupling capacitors to reduce voltage variations in a power system.
The continuing push to increase the operating speed of an integrated circuit while at the same time lowering the integrated circuit""s bus voltage has created the need for an integrated circuit power bus having higher current capability and tightly toleranced voltage levels. The extremely rapid switching rates of the discrete components which make up current integrated circuits can cause current transients on the power bus lasting into the nanoseconds. By contrast, the typical power supply driving the power bus has a current transient reaction time in the microseconds. Moreover, the lowering of the logic voltage levels requires a power bus to deliver a stable voltage signal having a minimum of voltage level variation. Consequently, power bus stability, in terms of current response and voltage level fluctuation, becomes a significant issue in the design of an integrated circuit.
One manner in which the issue of power bus stability has been addressed is with the insertion of decoupling capacitors between the power bus and the logical components making up an electronic device. A step like function is the conventional manner in which decoupling capacitors are inserted into the electronic device to provide power bus stability. In this approach, decoupling capacitors are placed into an electronic device layout using a sequence of steps to produce a grid-like decoupling capacitor layout. Consequently, the structured placement of the decoupling capacitors adds power bus stability, but at the cost of an increase in the area required for the layout of the electronic device. In addition, the step like placement of decoupling capacitors introduces gate placement constraints on the design and the designer. Such constraints include where to place logical components having timing limitations and the often difficult task of maintaining optimum wire lengths derived by the quadratic placer.
The structured placement of decoupling capacitors also hinders the electronic device that utilizes control blocks of random logic. The reason being the random switching of the components that makes up a control block of random logic. Because of the random switching of the components, it is difficult to measure average power consumption. Thus, the control block of random logic having above-average power consumption does not have the properly sized decoupling capacitance to support its power consumption needs. Consequently, the control block of random logic having an above average consumption is prone to event upsets caused by power bus instability.
The present invention addresses the above-described limitations of the conventional structured placement of decoupling capacitors in an electronic device. In particular, the present invention provides a drive strength control facility for evaluating the localized power consumption of components in an electronic device in order to determine the decoupling capacitor requirements of the design.
In one embodiment of the present invention, a method is practiced that provides a representation of an electronic device that contains one or more cells, where each cell can contain a single logical component of the electronic device. Based on the logical component contained in a cell, the drive strength facility is able to determine a drive strength for the selected cell. The drive strength calculated for the selected cell represents the current necessary to drive the logical component of the cell under full load conditions.
By grouping cells located in proximity to each other and summing the drive strengths of each cell in the group, a cumulative drive strength for the group of cells is determined. Should the cumulative drive strength for the group of selected cells exceed a defined threshold, the selected cells are flagged as requiring a decoupling capacitor.
Once the drive strength facility has identified the cell groupings requiring decoupling capacitors, the flagged cells are again examined by the drive strength facility. In this examination, the drive strength facility determines if sufficient area is available to insert a decoupling capacitor within a specified distance of the cell grouping. If component density in the particular cell grouping prohibits placement of a decoupling capacitor, the drive strength facility reviews the layout of the electronic device to determine whether sufficient space may be created by the shifting of one or more cells in a particular row.
The above-described approach avoids the problems associated with placing decoupling capacitors in a structured sequential manner. The present invention reduces decoupling capacitor usage, which can result in a design cost reduction, along with a reduction of area in electronic device allocated to decoupling capacitors, and also allows a circuit designer to target an area of an electronic device that may be susceptible to event upsets caused by voltage level variations on the power bus. As a result, the electronic device may have a smaller overall profile, or alternatively, may be enhanced with additional capability or functionality without increasing device size.
In accordance with another aspect of the present invention, a method is practiced for determining the decoupling capacitor needs of an electronic device that considers which cells within a cell grouping are active during a given clock phase. In this way, total component area in the cell grouping does not drive the decoupling capacitor requirements for the grouping. By identifying which logical components are active during a first phase of the clock cycle, and which logical components are active during the second phase of the clock cycle, results in a more accurate indication of current draw for the selected group of cells.
Thus, for a given cell grouping, the drive strength facility may calculate a first cumulative drive strength for the components in the cell grouping that are active during the first phase of the clock signal, and calculate a second cumulative drive strength for the components in the grouping that are active during the second phase of the clock signal. If the first cumulative drive strength exceeds a first threshold value, the group of cells is flagged to indicate the requirement of a decoupling capacitor. In like manner, if the second cumulative drive strength exceeds a second threshold, the cells are flagged to indicate the need of a decoupling capacitor. As a result, the sizing of the decoupling capacitor is based on current draw as opposed to total surface area consumed by the selected components.
In accordance with a further aspect of the present invention, a system is provided for determining the decoupling capacitor usage requirements of a selected electronic device. The system includes a display to view a layout of the electronic device, an input device for use by a system operator, a processor for executing instructions in response from the system operator, and a drive strength facility for determining the decoupling capacitor needs for the electronic device represented on the display. In response to input from the system operator, the drive strength facility examines the electronic device layout and indicates to the system operator a cell or a group of cells requiring a decoupling capacitor. The drive strength facility may indicate the cells requiring a decoupling capacitor by highlighting the cells in one or more colors, or by outlining the cells in one or more colored borders.
By providing a visual indication of the cells or group of cells requiring decoupling capacitors, the system operator may visually track the progress of the drive strength facility. In addition, the operator can monitor the placement of decoupling capacitors in the electronic device and intervene should a cell row of the design be too dense to insert a decoupling capacitor.
The above-described system allows decoupling capacitors to be placed in an electronic device layout with minimal impact to device timing requirements and wire length constraints. Consequently, the layout of timing sensitive logical components or level sensitive logical components does not have to be designed around a fixed decoupling capacitor pattern. The system provides the benefit of placing the decoupling capacitor where needed as dictated by the layout of the electronic device, thus avoiding the burden of having to insert decoupling capacitors in a structured sequential manner. .
In accordance with a further aspect of the present invention, a computer-readable medium provides instructions to an electronic device capable of reading the medium with a method for determining where to insert a decoupling capacitor in an electronic device using a calculated drive strength for one or more cells containing a component. Further, the computer-readable medium allows a computer system to distinguish between cells of logical components that are operative in a first clock phase from cells of logical components that are operative in a second clock phase. This method provides a more accurate drive strength calculation of the current necessary to drive the cell grouping under full-load conditions. By accurately predicting the drive strength required for a cell grouping, decoupling capacitors can then placed in or near the cell grouping identified as needing a decoupling capacitor. As a result, decoupling capacitor usage is minimized, which results in less area of an electronic device consumed by decoupling capacitors and an attributable cost savings.